1. Field of the Invention
The present invention relates to a dual storage apparatus which includes a memory for retaining data and an input/output system for the memory, both of which are dualized to improve reliability, and to a control method for the dual storage apparatus.
2. Description of the Related Art
Currently, the scope within which computers are needed industrially has been expanded and improved reliability is demanded for the computers. One type of reliability that is demanded for a computer is fault tolerance that guarantees that the computer can operate continuously even when a resource used in the computer (such as a CPU (Central Processing Unit), a memory, a hard disk, etc) has become defective, and another one is error tolerance that is an ability to be able to detect and correct a data error such as a bit invert generated in the course of transmission of information.
As one of the methods of improving the reliability demanded for a computer, multiplexing of the resources can be listed. For example, according to Japanese Patent Application Laid-Open Publication Nos. 1987-140153, 1992-149653, 1982-101950 and 1996-297588, configurations are described each of which has a memory dualized and identical data are written respectively into each of the counterpart memories included in the dual memory, the two (2) sets of data read from the counterpart memories respectively are compared with each other when the data have been read, and the set of data to be used for processing are selected.
Therefore, the fault tolerance can be improved because, even when one (1) counterpart memory has become defective, the data stored in the other counterpart memory can be used. In addition, because the date can not be used until the two (2) sets of data read from the dual memory coincide, detection/correction of errors in the data are executed during the comparison, thereby, the error tolerance can be improved.
A memory is controlled by a memory controller that processes read requests and write requests issued to the memory. In recent years, an LSI (Large Scale Integration) used in this memory controller has a complicated configuration due to the increase in capacity of a DIMM (Dual Inline Memory Module) and grow in the speed of data transfer. Therefore, the possibility that errors occur in the LSI and the possibility that the LSI is affected by the exterior environment through, for example, disturbance have become high.
When memories are dualized, the input/output system for each of the memories is also dualized and a memory controller is provided to each counterpart input/output system. Then, in general, two (2) memory controllers operate symmetrically (i.e., being synchronized). However, the controllers provided respectively to the counterpart input/output systems may operate differently from each other because of errors having occurred internally or disturbance even though the LSIs are those that operate symmetrically (i.e., being synchronized) under completely same conditions.
When the operation of the counterpart memory controllers in the dual memory becomes asymmetry (not being synchronized), phenomena such as, for example, a timing lag between the sets of data, loss of data, wrong order of data may occur to the computer. For example, when the data have been read, the two (2) sets of data read from the counterpart memories do not coincide only because of a timing lag between the sets of data. In this case, both sets of data themselves have not been destroyed, however, the computer can not determine which set of data should be used for processing. Therefore, continuous operation of the computer becomes impossible.
As described above, the prior art has a problem that, even when a memory is dualized, the operation of the computer is required to stop due to the malfunction of an LSI used in the memory controller and, then, the continuous operation of the computer becomes impossible even when the memory is dualized, therefore, the reliability demanded for the computer is degraded.